1. Field of the Invention
This invention pertains to the detection of the loss of a digital clock signal, and more particularly to the detection of the loss of an active system clock signal in a system implementing multiple clock signals by referencing the active clock signal to selected inactive clock signals, and further pertains to the ability to switch from the faulty clock signal to an operational clock signal upon detection of the loss of the faulty clock signal.
2. Description of the Prior Art
The present invention monitors for the loss of redundant clock signals. A plurality of redundant clock signal sources are used to ensure continued operation of a digital system, and the present invention monitors each of the redundant clock signals, and switches from a failed clock signal source to an operational clock signal source upon detection of the failed clock signal.
Prior art has shown the detection of two clock signals which are out of phase from one another, where one clock signal is derived from a Voltage Controlled Oscillator (VCO), and the other is a reference signal. One such arrangement is shown in U.S. Pat. No. 4,135,165, by Coe, issued Jan. 16, 1979, and detects when the phase difference between the two signals has deviated by a maximum predetermined amount, and resynchronizes them. Another arrangement which concerns clock signal loss detection is shown in U.S. Pat. No. 4,968,951, by Itaya et al., issued Nov. 6, 1990, which discloses a method of restarting a Voltage Controlled Oscillator (VCO) in a phase-locked loop that has stopped oscillating due to characteristics of a wide band oscillation VCO. It further discloses a method of overcoming AC noise problems which cause the VCO to remain in the halted state. Therefore, a design such as Itaya et al. is to be used in conjunction with a VCO in a phase-locked loop where the VCO stops oscillating due to inherent circuit characteristics.
The present invention does not monitor for oscillator signal discontinuation for a single oscillator in a phase-locked loop as in Itaya et al., nor is it a phase detection and synchronization circuit for a VCO in a phase-locked loop as in Coe. The present invention was developed to simultaneously monitor multiple clock signals which provide clock signal redundancy to a digital system. Auxiliary or redundant clock signals may be used in a system which requires a high reliability of clock signal availability. In such a system, the loss of one clock signal must not result in a system shutdown. The present invention monitors each of the clock signals, selects a clock signal source to generate the active system clock signal, and switches to an operational clock signal source upon detection of the loss of the clock signal which is driven by the active system clock signal source.
The present invention also allows the selection of more than one clock signal source to supply the active system clock signal. This is desirable in a system which not only requires continuous clock signal capability, but also requires circuit load redundancy. In such a system, redundant loads may be clocked by separate synchronized clock signals, so that the failure of one circuit load will not result in data loss, since the redundant load would still be operational. This type of a system would require a separate clock signal for each circuit load, so that the loss of one clock signal or the loss of a circuit load would not result in a system failure. The preferred embodiment of the present invention monitors multiple clock signals, and selects two clock signal sources as redundant active system clock signal sources. Upon detection of a clock signal loss, a new clock signal will be selected. Since all redundant clock signals are simultaneously monitored for clock signal loss (even when its associated clock signal source is not selected as the active system clock signal source), the new clock signal can be selected with minimal delay.
The invention monitors for clock signal loss without the need for a separate reference clock. Since redundant clock signals are provided, the clock signals are compared to each other rather than a reference clock. A voting scheme is then used to determine which clock signal has actually failed. By comparing the clock signals to each other rather than to a reference clock signal, extra component costs can be avoided, and the design is simplified.